Mnemostasis emblem

Mnemostasis

Stays true.

A self-calibrating in-memory AI accelerator that senses analog drift and restores it in place — so inference accuracy holds for the life of the device.

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In-memory compute · drift compensation

Memory, held in equilibrium.

Mnemostasis is a self-calibrating in-memory AI accelerator. It senses analog conductance drift and restores it in place — so inference accuracy holds across the full life of the device.

The problem

Analog compute is fast. Left alone, it forgets.

Compute-in-memory runs a neural network's matrix math inside the memory itself — weights stored as the conductance of resistive cells, multiply-accumulate done in the physics. The speed and energy wins are real. So are three failure modes that quietly erode them.

Drift

Weights wander

Cell conductance shifts over time and under read stress. A weight set to G becomes G ± ΔG, and accuracy slides downhill with no built-in correction.

IR drop

Scale distorts the sum

Resistance along long rows and columns skews the summed current — error grows with array size, capping how large a useful tile can be.

Conversion

The ADC eats the win

Analog-to-digital readout tends to dominate energy and area, eroding the very efficiency that made in-memory compute worth building.

The proof

Accuracy that doesn't decay with the device.

Without compensation, top-1 accuracy slides as cells drift over billions of inferences. Mnemostasis holds it. Drag across the device lifetime to compare.

Accuracy over lifetime
Mnemostasis
top-1 held
Uncompensated
top-1 drifted
Advantage
at —
↔ drag to move across the device lifetime

Curves are illustrative of the compensation behaviour, not measured silicon results.

Digital acceleratorAnalog CIM (uncompensated)Mnemostasis
Energy / inferenceHighLowLow
Accuracy over lifeStableDegrades with drift Held in tolerance
Array scalePower-boundIR-drop-boundSegmented bitlines
Self-calibrationNone In-situ, per tile
How it works

A closed loop that keeps memory true.

Each tile carries its own reference cells of known conductance. Mnemostasis reads them, measures how far the array has drifted, and restores it in place — during idle cycles, while neighbouring tiles keep inferring.

01

Sense. Read the reference column.

Known-conductance reference cells share the tile's process corner and temperature, so their deviation is a true reading of the drift the weights are feeling.

02

Restore. Nudge cells back to target.

When the drift metric crosses threshold, partial programming pulses with read-back-and-verify walk each cell's conductance toward target — no off-array weight reload for routine drift.

03

Hold. Resume, accuracy intact.

A controller schedules restoration by drift metric or inference count, within a pulse budget that never starves inference — so accuracy stays inside a bounded tolerance for the device's life.

01 02 03 EQUILIBRIUM
What's inside

The compensation is the architecture.

ACTPWM REF SEGMENTED BITLINE · ∑ charge ADC ×1 SENSE + RESTORE partial-pulse restore SCHEDULER

Per-tile reference column

Local, in-situ drift sensing instead of a global guess. Every tile measures its own drift against cells it can trust — they live in the same silicon.

Segmented bitlines

Charge-domain accumulators break each column into segments, bounding IR drop and letting one lower-resolution converter be shared.

Drift-aware co-scheduler

Maps layers to tiles and times restoration by drift metric or accumulated inference count, catching slow drift before accuracy crosses the floor.

Reference configuration

One representative tile.

Array / tile
256 × 256 non-volatile resistive cells
Weight precision
4–6 bit, signed via differential column pairs
Activation encoding
8-bit pulse-width-modulated wordlines
Reference cells
16 per tile, spanning the usable conductance range
Bitline segments
4, with charge-domain accumulation and a shared ADC
Restoration
In-situ partial-pulse, read-back-and-verify, budgeted to idle intervals
Cell technology
Technology-agnostic — RRAM, PCM, or floating-gate
Accuracy retention
Held within a bounded tolerance past 10⁹ inferences
Concurrency
Per-tile restore during idle; neighbouring tiles keep inferring

Representative figures for a reference design; final parameters depend on device and process selection.

The cybernetic tradition

Homeostasis, written into the hardware.

Strip away the silicon and Mnemostasis is a feedback loop of the oldest kind: it measures how far a system has drifted from its setpoint and acts to close the gap — the same negative feedback that holds a body’s temperature steady. Norbert Wiener named the principle in 1948 — cybernetics, the study of control and communication in the animal and the machine.

TARGET G Σ + RESTORE controller MEMORY ARRAY plant drift conductance REFERENCE SENSE
Wiener · 1948

Negative feedback

Sense the error, drive it to zero. The reference column measures drift; restoration cancels it. The loop’s whole job is to keep the error small.

Cannon · homeostasis

A regulated setpoint

A variable held steady against disturbance. Here the variable is conductance, the disturbance is drift, and the setpoint is the programmed weight.

Ashby · ultrastability

Essential variables, bounded

Cross a threshold, trip a corrective step. Mnemostasis holds accuracy inside tolerance in exactly that way.

Lineage, not label: engineers will file this under control systems and neuromorphic design — but the governing idea is pure cybernetics, a machine that regulates itself toward equilibrium.

Where it matters

Built for inference that has to last.

Drift compensation earns its keep wherever a device runs for years and can't be recalled to reload its weights.

Automotive

ADAS & autonomy

A decade in the field across wide thermal cycling. Perception accuracy can't be allowed to quietly drift between service intervals.

Medical

Implantable & bedside edge

Devices that can't be retrieved to recalibrate. Inference has to stay trustworthy for the life of the implant.

Industrial

Always-on monitoring

24/7 inference at the edge means drift accumulates fast. Self-restoration keeps lines and sensors honest without downtime.

Aerospace & defense

Long missions, no service

Harsh environments, long deployments, zero maintenance windows — exactly where uncompensated analog accuracy fails.

Roadmap

From provisional to silicon.

01

IP & architecture

Provisional patent in preparation; the protectable combination defined and the §101 posture set.

02

Device emulation

Behavioural and device-level models of drift and restoration, validating the accuracy-retention claim.

03

Test chip

A small-array silicon prototype proving the sense-and-restore loop in real cells.

04

Tile tape-out

Full-tile integration with segmented bitlines and the shared converter.

05

Partner silicon

Qualification and integration into partner accelerators and edge platforms.

Intellectual property

Built to be protected.

The defensible position isn't any single part — it's the combination: an on-tile reference column, in-situ partial-pulse restoration with write-verify, and inference-count-aware scheduling, working together inside the array.

Mnemostasis is framed for patent eligibility as a hardware improvement — a technological solution to a technological problem — rather than as a claim over the underlying neural-network math. Apparatus claims lead; the restoration loop, not the matrix multiply, carries the inventive weight.

Patent-pending design · provisional application in preparation. Subject to prior-art and freedom-to-operate review.

Reference-column sensingIn-situ restorationWrite-verify loopSegmented bitlineDrift-aware scheduling
Questions

The things engineers ask first.

Does restoration interrupt inference?+

No. Restoration runs per tile during that tile's idle intervals, within a pulse budget, while neighbouring tiles keep inferring. The scheduler is built so calibration never starves the workload.

Which memory technology does it need?+

It's technology-agnostic. The reference-column and partial-pulse approach applies to RRAM, phase-change memory, or floating-gate cells — anything where a weight is held as an analog conductance that can drift and be re-tuned.

Is this for training or inference?+

Inference. Weights are loaded once; Mnemostasis keeps them true. The invention deliberately does not claim the training math — that framing also keeps it on the right side of patent-eligibility rules for hardware.

How is accuracy actually guaranteed over the device's life?+

Reference cells of known conductance are read continuously; their deviation gives a true per-tile drift metric. When it crosses threshold, restoration pulls cells back to target. Accuracy is held inside a stated tolerance rather than allowed to decay.

What makes the IP defensible?+

A combination claim led by apparatus claims: reference-column sensing plus in-situ write-verify restoration plus inference-count-aware scheduling. The inventive weight sits on the restoration loop — a concrete hardware improvement — not on the matrix multiply.

Mnemostasis Get in touch

Memory that doesn't fade.

For partnership, licensing, or technical detail on the architecture and its IP posture — we'd be glad to talk.

contact@mnemostasis.com